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366 Channel Express RX2 8/1500
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Model 366 - Channel Express RX2 8/1500
Model 366 - Channel Express RX2 8/1500
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 Model 366 (PDF 897Ko)

Features
  • Available in XMC and PCIe form factors
  • Dual 8-bit analog-to-digital converter (ADC)
  • 0.6 to 1.5 GHz sample clock frequency
  • Xilinx Virtex-5 LXT or SXT FPGA
  • 32 Mbytes SRAM / 128 Mbytes SDRAM
  • On-board fixed frequency synthesizer
  • FPGA core library for data interfaces
  • PCI Express (PCIe) eight lane (x8) bus
  • Bus master with scatter-gather DMA
  • Windows, Linux, VxWorks drivers & API
  • Reference design with source code
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Description
  • The Channel Express product family provides the ideal platform to rapidly field application specific signal acquisition and generation functions minus the expense of custom hardware development. All of the products share a common FPGA processing architecture and code base with different interface options tailored to a variety of market needs.

    The Model 366 is designed around the National Semiconductor ADC08D1520 8-bit ADC. The 1.5 GHz sample clock is supplied by either an on-board frequency synthesizer or an external source. The frequency synthesizer can be phase locked to the local 10 MHz TCXO or an external reference can be used to achieve system-wide phase coherence.

    The analog ADC inputs can be either AC or DC coupled to the external environment. The AC coupled configuration supports direct IF sampling (bandpass sampling) beyond the first Nyquist zone. The DC coupled option allows operating frequencies to approach zero without attenuation. The FPGA is selected from the Xilinx Virtex-5 high performance logic (LXT) or signal processing (SXT) platforms. A variety of size and speed grade options are offered to optimize the price/performance ratio over a wide range of applications.

    The FPGA communicates with the host processor through an integrated endpoint block for PCI Express, leaving the majority of logic uncommitted for customer applications.

    The Model 366 includes up to 32 Mbytes of QDR SRAM and 128 Mbytes of DDR SDRAM. The QDR SRAM interfaces to the FPGA through separate 16-bit read and write ports to achieve a combined 8 Gbytes/sec data transfer rate. This allows high-speed signal acquisition or generation independent of PCIe bus throughput. A 32-bit DDR SDRAM is available to meet lower rate, high-capacity storage needs.
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