The PX14400D is a dual channel high speed data acquisition board that provides a combination of high speed and high resolution sampling along with a very large memory capacity. This board is a companion to Signatec’s PX14400A and is intended primarily for applications that require DC capability. The analog input bandwidth is set to 200 MHz via 3-pole Bessel filters on each input channel.
The PX14400D has a primary sample-data RAM bank of 512 MB memory that may be used as an exceptionally large FIFO for acquiring non-stop, continuous data directly to either the PCI Express (PCIe) bus or the SAB. In Buffered Acquisition Mode (where the 512 MB RAM FIFO is used) the PX14400D is capable of sustaining 1400 MB/s over the PCIe bus. Significant test data has shown that recording with large FIFO buffering can be continuous at these rates even when operating in traditional non real-time environments such as the Windows operating system.
The PX14400D employs up to two Virtex-5 FPGAs, where one of the FPGAs is available as an option for customers to implement their own custom in-line signal processing. A standard FIFO interface to the Signatec specific logic portion of the PX14400D along with control flags, an example program using the FIFOs/flags and a programmer’s manual are provided with the optionally available PX14400D Firmware Development Kit. The PX14400D can be ordered either with or without this 2nd user accessible FPGA. Boards without the user FPGA are -DR (data recording only) models and boards with the user FPGA are -SP (signal processing) models.
The PX14400D has 2 selectable-gain voltage ranges for each channel. The full scale voltages are 1.2 volts and 400 millivolts. Inline 6dB attenuators are available that effectively change the levels to 2.4 volts and 800 millivolts. The DC offset for each channel is individually adjustable via 12-bit DACs. The adjustment range is sufficient so that the input voltage span can be set for unipolar positive, unipolar negative, bipolar, or any value in between.
A frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 20 to 400 MHz (except 277 MHz to 308 MHz), offering maximum flexibility for sampling rate selection. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source.
Up to five PX14400D boards may be interconnected in a Master/Slave configuration via a ribbon cable that connects at the top of the board. In this configuration, the Master board drives the clock and trigger signals for the Slave boards so that data sampling on all boards occurs simultaneously.