PCI66-18AI8SS8AO8 - 16-Ch, 500kS/s, 18-bit, PCI Board

Main features

  • 8 Differential 18-Bit Analog Input Channels
  • DC to 500KSPS Sample Rate per Channel
  • DC Accuracy: 0.005% Vsig + 0.003% FSR
  • Group Delay: 8uS, 0-500KSPS, Maximum
  • Continuous-Time 4-Pole Lowpass Filter; Selectable as Fc = 80kHz or 200kHz. Custom frequencies available.
  • Inputs are software-configurable with or without 0-20ma current-loop input termination;
  • 500 Ohms, 0.05%, 0.4 Watt, Individually selectable for each input channel
  • 100 dB Dynamic Range; Typical to 100 kHz with Fsamp = 400ksps
  • 92 dB SINAD; Typical to 100 kHz with Fsamp = 400ksps
  • 8 Single-ended or 3-Wire Differential 18-Bit Analog Output Channels
  • DC to 500KSPS Sample Rate per Channel
  • DC Accuracy: 0.005% Vsig +0.003% FSR
  • Group Delay: 10us, 0-500KSPS, Maximum
  • 95 dB Dynamic Range, Typical to 1MHz with Fsamp = 400ksps
  • 90 dB SINAD, Typical to 1MHz with Fsamp = 400ksps
  • Common Input/Output Characteristics:
  • Software-Selectable Input/Output Ranges: ±5V, ±10V, 0 to +10V.
  • Independent Input and output range selection. All inputs share a common input range, and all outputs share a common output range.
  • Synchronous or Independent Input/Output Clocking
  • Independent 1-MByte Input and Output FIFO Buffers; 2 MBytes total;
  • Optional 2-MByte Input and Output Buffers;  4 MBytes Total
  • Internal Sample Rate Generators
  • 32-Bit Event Timer
  • Hardware Sync and Clock I/O for Multiboard Synchronization
  • 66/33MHz PCI support
  • Conforms to PCl Bus Specification, Revision 2.3, with Universal
  • Signaling Standard Full-Length PCI Form Factor
  • DMA Engine Supports Block-Mode Transfers in Two Channels
  • On-demand Autocalibration Ensures DC Precision as well as AC performance
  • Integrated DC/DC Conversion and Dual Regulation for Internal Supply Voltages
Price request Datasheet

The PCI66-18AISS8AO8 is a precision 18-Bit analog I/O product that provides eight simultaneously sampled input channels and eight simultaneously clocked output channels, Inputs and outputs can be clocked synchronously or independently at rates up to 500 KSPS per channel, and are supported by independent 512K-Sample FIFO data buffers. Both continuous and burst clocking modes are supported, and voltage ranges are independently software-selectable as ±10V, ±5V, ±2.5V, 0 to +10V or 0 to +5V for inputs and outputs. Clocking and triggering rates can be derived from internal rate generators, or from external clock and trigger sources to support the synchronous operation of multiple boards.

Input sampling employs successive-approximation (SAR) conversion, which avoids the high latency or minimum-rate limitations of delta-sigma and pipelined conversion schemes. Each analog input channel can be individually programmed to provide termination for current-loop instrumentation. The analog outputs use a weighted-DAC R-2R configuration which, like the analog inputs, minimizes latency and has no minimum clocking rate. The outputs can be software-configured for either single-ended or 3-wire differential operation.

On-demand autocalibration determines and applies error correction for all input and output channels, and a selftest input switching network permits board integrity to be verified by the host. Eight bidirectional digital I/O lines are programmable as inputs or outputs.

PCI66-18AI8SS8AO816-Ch, 500kS/s, 18-bit, PCI Board

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